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Prediction-Based Parallel Gate-Level Timing Simulation Using Spatially Partial Simulation Strategy
Jaehoon Han, Seiyang Yang KIPS Transactions on Computer and Communication Systems,
Vol. 8, No. 3, pp. 57-64,
Mar.
2019
https://doi.org/10.3745/KTCCS.2019.8.3.57
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation, Timing Simulation
https://doi.org/10.3745/KTCCS.2019.8.3.57
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation, Timing Simulation
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